DesignCompiler（DC）逻辑综合工具权威用户手册（DesignCompilerUserGuideVersionH-2013.03）摘要：本文是SynopsysDesignCompilerH-2013.03版官方用户指南，系统讲解数字逻辑综合全流程。内容涵盖工具基础操作、库配置、设计读入与层级管理、环境与约束定义、时序/面积/功耗优化及问题调试。详细介绍Topographical物理感知综合、多角多模式（MCMM）、接口逻辑模型（ILM）、层次化抽象与UPF低功耗流程，支持自上而下/自下而上混合编译策略。指南包含完整命令语法、约束设置、时序修复、物理约束导入与结果分析方法，配套工程案例与脚本规范，为数字IC前端工程师提供从RTL到门级网表的标准化综合实践指导。DesignCompiler®UserGuideVersionH-2013.03,March2013CopyrightNoticeandProprietaryInformationCopyright◎2013Synopsys,Inc.Allrightsreserved.ThissoftwareanddocumentationcontainconfidentialandproprietaryinformationthatisthepropertyofSynopsys,Inc.Thesoftwareanddocumentationarefurnishedunderalicenseagreementandmaybeusedorcopiedonlyinaccordancewiththetermsofthelicenseagreement.Nopartofthesoftwareanddocumentationmaybereproduced,transmitted,ortranslated,inanyformorbyanymeans,electronic,mechanical,manual,optical,orotherwise,withoutpriorwrittenpermissionofSynopsys,Inc.,orasexpresslyprovidedbythelicenseagreement.DestinationControlStatementAlltechnicaldatacontainedinthispublicationissubjecttotheexportcontrollawsoftheUnitedStatesofAmerica.DisclosuretonationalsofothercountriescontrarytoUnitedStateslawisprohibited.Itisthereader'sresponsibilitytodeterminetheapplicableregulationsandtocomplywiththem.DisclaimerSYNOPSYS,INC.,ANDITSLICENSORSMAKENOWARRANTYOFANYKIND,EXPRESSORIMPLIED,WITHREGARDTOTHISMATERIAL,INCLUDING,BUTNOTLIMITEDTO,THEIMPLIEDWARRANTIESOFMERCHANTABILITYANDFITNESSFORAPARTICULARPURPOSE.TrademarksSynopsysandcertainSynopsysproductnamesaretrademarksofSynopsys,assetforthathttp://www.synopsys.com/Company/Pages/Trademarks.aspx.Allotherproductorcompanynamesmaybetrademarksoftheirrespectiveowners.Synopsys,Inc.700E.MiddlefieldRoadMountainView,CA94043www.synopsys.comCopyrightStatementfortheCommand-LineEditingFeatureCopyright◎1992,1993TheRegentsoftheUniversityofCalifornia.Allrightsreserved.ThiscodeisderivedfromsoftwarecontributedtoBerkeleybyChristosZoulasofCornellUniversity.Redistributionanduseinsourceandbinaryforms,withorwithoutmodification,arepermittedprovidedthatthefollowingconditionsaremet:1.Redistributionsofsourcecodemustretaintheabovecopyrightnotice,thislistofconditionsandthefollowingdisclaimer.2.Redistributionsinbinaryformmustreproducetheabovecopyrightnotice,thislistofconditionsandthefollowingdisclaimerinthedocumentationand/orothermaterialsprovidedwiththedistribution.3.Alladvertisingmaterialsmentioningfeaturesoruseofthissoftwaremustdisplaythefollowingacknowledgement:ThisproductincludessoftwaredevelopedbytheUniversityofCalifornia,Berkeleyanditscontributors.4.NeitherthenameoftheUniversitynorthenamesofitscontributorsmaybeusedtoendorseorpromoteproductsderivedfromthissoftwarewithoutspecificpriorwrittenpermission.THISSOFTWAREISPROVIDEDBYTHEREGENTSANDCONTRIBUTORS"ASIS"ANDANYEXPRESSORIMPLIEDWARRANTIES,INCLUDING,BUTNOTLIMITEDTO,THEIMPLIEDWARRANTIESOFMERCHANTABILITYANDFITNESSFORAPARTICULARPURPOSEAREDISCLAIMED.INNOEVENTSHALLTHEREGENTSORCONTRIBUTORSBELIABLEFORANYDIRECT,INDIRECT,INCIDENTAL,SPECIAL,EXEMPLARY,ORCONSEQUENTIALDAMAGES(INCLUDING,BUTNOTLIMITEDTO,PROCUREMENTOFSUBSTITUTEGOODSORSERVICES;LOSSOFUSE,DATA,ORPROFITS;ORBUSINESSINTERRUPTION)HOWEVERCAUSEDANDONANYTHEORYOFLIABILITY,WHETHERINCONTRACT,STRICTLIABILITY,ORTORT(INCLUDINGNEGLIGENCEOROTHERWISE)ARISINGINANYWAYOUTOFTHEUSEOFTHISSOFTWARE,EVENIFADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGE.CopyrightStatementfortheLine-EditingLibraryCopyright◎1992SimmuleTurnerandRichSalz.Allrightsreserved.ThissoftwareisnotsubjecttoanylicenseoftheAmericanTelephoneandTelegraphCompanyoroftheRegentsoftheUniversityofCalifornia.Permissionisgrantedtoanyonetousethissoftwareforanypurposeonanycomputersystem,andtoalteritandredistributeitfreely,subjecttothefollowingrestrictions:1.Theauthorsarenotresponsiblefortheconsequencesofuseofthissoftware,nomatterhowawful,eveniftheyarisefromflawsinit.2.Theoriginofthissoftwaremustnotbemisrepresented,eitherbyexplicitclaimorbyomission.Sincefewuserseverreadsources,creditsmustappearinthedocumentation.3.Alteredversionsmustbeplainlymarkedassuch,andmustnotbemisrepresentedasbeingtheoriginalsoftware.Sincefewuserseverreadsources,creditsmustappearinthedocumentation.4.Thisnoticemaynotberemovedoraltered.PrefaceThisprefaceincludesthefollowingsections:•AboutThisManual•CustomerSupportAboutThisManualTheDesignCompilerUserGuideprovidesbasicsynthesisinformationforusersoftheDesignCompilertools.Thismanualdescribessynthesisconceptsandcommands,andpresentsexamplesforbasicsynthesisstrategies.Thismanualdoesnotcoverasynchronousdesign,I/Opadsynthesis,testsynthesis,simulation,orback-annotationofphysicaldesigninformation.TheinformationpresentedheresupplementstheSynopsyssynthesisreferencemanualsbutdoesnotreplacethem.SeeotherSynopsysdocumentationfordetailsabouttopicsnotcoveredinthismanual.ThismanualsupportstheSynopsyssynthesistools,whethertheyarerunningundertheUNIXoperatingsystemortheLinuxoperatingsystem.ThemaintextofthismanualdescribesUNIXoperation.AudienceThismanualisintendedforlogicdesignersandengineerswhousetheSynopsyssynthesistoolswiththeVHDLorVeriloghardwaredescriptionlanguage(HDL).Beforeusingthismanual,youshouldbefamiliarwiththefollowingtopics:•High-leveldesigntechniques•ASICdesignprinciples•Timinganalysisprinciples•FunctionalpartitioningtechniquesRelatedPublicationsForadditionalinformationaboutDesignCompiler,seethedocumentationonSolvNetatthefollowingaddress:https://solvnet.synopsys.com/DocsOnWebYoumightalsowanttoseethedocumentationforthefollowingrelatedSynopsysproducts:•DesignVision•DesignWarecomponents•DFTCompilerandDFTMAX•DCExplorer•PrimeTime•PowerCompiler•HDLCompiler•ICCompilerReleaseNotesInformationaboutnewfeatures,changes,enhancements,knownlimitations,andresolvedSynopsysTechnicalActionRequests(STARs)isavailableintheDesignCompilerReleaseNotesinSolvNet.ToseetheDesignCompilerReleaseNotes,1.GototheDownloadCenteronSolvNetlocatedatthefollowingaddress:https://solvnet.synopsys.com/DownloadCenter2.SelectDesignCompiler,andthenselectareleaseinthelistthatappears.ConventionsThefollowingconventionsareusedinSynopsysdocumentation.CustomerSupportCustomersupportisavailablethroughSolvNetonlinecustomersupportandthroughcontactingtheSynopsysTechnicalSupportCenter.AccessingSolvNetSolvNetincludesaknowledgebaseoftechnicalarticlesandanswerstofrequentlyaskedquestionsaboutSynopsystools.SolvNetalsogivesyouaccesstoawiderangeofSynopsysonlineservicesincludingsoftwaredownloads,documentation,andtechnicalsupport.ToaccessSolvNet,gotothefollowingaddress:https://solvnet.synopsys.comIfprompted,enteryourusernameandpassword.IfyoudonothaveaSynopsysusernameandpassword,followtheinstructionstoregisterwithSolvNet.IfyouneedhelpusingSolvNet,clickHELPinthetop-rightmenubar.ContactingtheSynopsysTechnicalSupportCenterIfyouhaveproblems,questions,orsuggestions,youcancontacttheSynopsysTechnicalSupportCenterinthefollowingways:•OpenasupportcasetoyourlocalsupportcenteronlinebysigningintoSolvNetathttps://solvnet.synopsys.com,clickingSupport,andthenclicking“OpenASupportCase.”•Sendane-mailmessagetoyourlocalsupportcenter.❍E-mailsupport_center@synopsys.comfromwithinNorthAmerica.❍Findotherlocalsupportcentere-mailaddressesathttp://www.synopsys.com/Support/GlobalSupportCenters/Pages•Telephoneyourlocalsupportcenter.❍Call(800)245-8005fromwithinNorthAmerica.❍Findotherlocalsupportcentertelephonenumbersathttp://www.synopsys.com/Support/GlobalSupportCenters/Pages1IntroductiontoDesignCompilerTheDesignCompilertoolisthecoreoftheSynopsyssynthesisproducts.DesignCompileroptimizesdesignstoprovidethesmallestandfastestlogicalrepresentationofagivenfunction.ItcomprisestoolsthatsynthesizeyourHDLdesignsintooptimized,technology-dependent,gate-leveldesigns.Itsupportsawiderangeofflatandhierarchicaldesignstylesandcanoptimizebothcombinationalandsequentialdesignsforspeed,area,andpower.DesignCompileralsoprovidestopographicaltechnology,whichallowsyoutoaccuratelypredictpost-layouttiming,area,andpowerduringRTLsynthesiswithouttheneedfortimingapproximationsbasedonwireloadmodels.ItusesSynopsysplacementandoptimizationtechnologiestodriveaccuratetimingpredictionwithinsynthesis,ensuringbettercorrelationwiththefinalphysicaldesign.Inaddition,DesignCompilerprovidestheDesignCompilerGraphicaltool,whichoptimizesmulticorner-multimodedesignsandallowsyoutocreateandmodifyfloorplansusingfloorplanexploration.Thetoolalsoreducesroutingcongestion,anditimprovesareacorrelationwithICCompilerandruntimeinICCompiler.ForanoverviewofDesignCompiler,see•DesignCompilerintheDesignFlow•High-LevelDesignFlowTasks•DesignCompilerFamilyDesignCompilerintheDesignFlowYouuseDesignCompilerforlogicsynthesis,whichistheprocessofconvertingadesigndescriptionwritteninahardwaredescriptionlanguage,suchasVerilogorVHDL,intoanoptimizedgate-levelnetlistmappedtoaspecificlogiclibrary.Whenthesynthesizeddesignmeetsfunctionality,timing,power,andotherdesigngoals,youcanpassthedesigntoICCompilerforphysicalimplementation.Eventhoughthefollowingtermshaveslightlydifferentmeanings,theyareoftenusedsynonymouslyintheDesignCompilerdocumentation:•Synthesisistheprocessthatgeneratesagate-levelnetlistforanICdesignthathasbeendefinedwithahardwaredescriptionlanguage(HDL).SynthesisincludesreadingtheHDLsourcecodeandoptimizingthedesigncreatedfromthatdescription.•Optimizationisthestepinthesynthesisprocessthatimplementsacombinationoflibrarycellsthatbestmeetthefunctional,timing,area,andpowerrequirementsofthedesign.•CompileistheDesignCompilerprocessthatexecutesthesynthesisandoptimizationsteps.Afteryoureadinthedesignandperformothernecessarytasks,yourunthecompile_ultraorcompilecommandtogenerateagate-levelnetlistforthedesign.Figure1-1showsanoverviewofhowDesignCompilerfitsintothedesignflow.High-LevelDesignFlowTasksFigure1-2showsthehigh-leveldesignflowfromHDLcodingtophysicalimplementationinICCompiler.Theshadedareasindicatewherethedesignexplorationandsynthesistasksoccurintheflow.Thesynthesisdesignflowconsistsofthedesignexplorationstageandthefinaldesignimplementationstage.Inthedesignexplorationstage,youuseDCExplorertoperformwhat-ifanalysesofvariousdesignconfigurationsearlyinthedesigncycletospeedthedevelopmentofhigh-qualityRTLandconstraintsanddriveafaster,moreconvergentdesignflow.Inthedesignimplementationstage,youusethefullpowerofDesignCompilertosynthesizethedesign.Usingthehigh-leveldesignflowshowninFigure1-2,youperformthefollowingtasks:1.WriteanHDLdescriptionofyourdesigninVerilogorVHDL.UsegoodcodingpracticestofacilitatesuccessfulDesignCompilersynthesisofthedesign.2.Performdesignexplorationandfunctionalsimulationinparallel.❍Indesignexploration,useDCExplorerto(a)implementspecificdesigngoals,suchasdesignrulesandoptimizationconstraints,(b)detectmismatchesandmissingconstraints,and(c)resolvemismatchesanddesigndatainconsistencies.Youcanalsocreateandmodifyfloorplansearlyinthedesigncyclewithfloorplanexploration.❍Ifdesignexplorationfailstomeettiminggoalsbymorethan10percent,modifyyourdesigngoalsandconstraints,orimprovetheHDLcode.Thenrepeatbothdesignexplorationandfunctionalsimulation.❍Infunctionalsimulation,determinewhetherthedesignperformsthedesiredfunctionsbyusinganappropriatesimulationtool.❍Ifthedesigndoesnotfunctionasrequired,youmustmodifytheHDLcodeandrepeatbothdesignexplorationandfunctionalsimulation.❍Continueperformingdesignexplorationandfunctionalsimulationuntilthedesignisfunctioningcorrectlyandiswithin10percentofthetiminggoals.3.PerformdesignimplementationsynthesisbyusingDesignCompilertomeetdesigngoals.Aftersynthesizingthedesignintoagate-levelnetlist,verifythatthedesignmeetsyourgoals.Ifthedesigndoesnotmeetyourgoals,generateandanalyzevariousreportstodeterminethetechniquesyoumightusetocorrecttheproblems.4.Afterthedesignmeetsfunctionality,timing,power,andotherdesigngoals,proceedtothephysicalimplementationstageinICCompiler.5.Analyzethephysicaldesign’sperformancebyusingback-annotateddata.Iftheresultsdonotmeetdesigngoals,resolvetheminICCompilerorreturntostep3.Iftheresultsmeetyourdesigngoals,youarefinishedwiththedesigncycle.SeeAlso•DesignCompilerintheDesignFlow•RunningaSynthesisFlowDesignCompilerFamilyTheDesignCompilerfamilyprovidesanintegratedRTLsynthesissolutiontoaddresstoday’schallengingICdesigns.UsingDesignCompilertools,youcan•Producefast,area-andpower-efficientICdesignsusingadvancedoptimizationsandsharedtechnologywithICCompilerplaceandroute•Predict,visualize,andalleviateroutingcongestion•Performfloorplanexplorationtocreateandmodifydesignfloorplans•Exploredesigntradeoffsinvolvingdesignconstraints,suchastiming,area,andpower,undervariousloading,temperature,andvoltageconditionsTolearnabouttheDesignCompilerfamilyofproducts,see•AboutDCUltra•AboutDesignCompilerGraphical•AboutDCExpert•AboutDCExplorer•AboutDesignVision•AboutDesignWareLibrary•AboutDFTCompilerandDFTMAX•AboutLibraryCompiler•AboutPowerCompilerAboutDCUltraAtthecoreoftheSynopsysRTLsynthesissolutionisDCUltra.DCUltraprovidesconcurrentoptimizationoftiming,area,power,andtestfortoday’shighperformancedesigns.DCUltraincludestopographicaltechnology,whichallowsyoutoaccuratelypredictpost-layouttiming,area,andpower,ensuringbettercorrelationwiththefinalphysicaldesign.DCUltraprovidesthefollowingfeatures:•PlacementandoptimizationtechnologiesthataresharedwithICCompilerplaceandroutetodriveaccuratetimingandareapredictionwithinsynthesis,ensuringabetterstartingpointforphysicalimplementation•Advanceddelayoptimizationalgorithms•Advancedarithmeticoptimization•Integrateddatapathpartitioningandsynthesiscapabilities•Advancedcriticalpathresynthesis•Registerretiming,theprocessbywhichthetoolmovesregistersthroughcombinationalgatestoimprovetiming•Advancedtiminganalysis•Supportformultivoltageandmultiplesupplydesigns•Infrastructuretosupportmulticoreexecutionforfasterruntimes•Supportforhierarchicalcompile(topdownorbottomup)•Fullandincrementalcompiletechniques•Sequentialoptimizationforcomplexflip-flopsandlatches•Command-lineinterfaceandgraphicaluserinterfaceSeeAlso•OverviewofTopographicalTechnologyAboutDesignCompilerGraphicalInadditiontoDCUltracapabilities,DesignCompilerGraphicalprovidesthefollowingfeatures:•Optimizationformulticorner-multimodedesigns•Reductionofroutingcongestionduringsynthesis•ImprovedareaandtimingcorrelationwithICCompiler•ImprovedruntimeandroutabilityinICCompiler•Physicalguidancetechnology,whichincludesenhancedplacementandthecapabilitytopassseedplacementtoICCompilertoimprovequalityofresults(QoR),correlation,androutability•AbilitytocreateandmodifyfloorplansusingfloorplanexplorationSeeAlso•UsingtheDesignCompilerGraphicalToolAboutDCExpertDCExpertprovidesoptimizationforarea,timing,andpowerusingwireloadmodelsfordelayestimation.DCExpertprovidesthefollowingfeatures:•Hierarchicalcompile(topdownorbottomup)•Fullandincrementalcompiletechniques•Sequentialoptimizationforcomplexflip-flopsandlatches•Timeborrowingforlatch-baseddesigns•Timinganalysis•Command-lineinterfaceandgraphicaluserinterfaceAboutDCExplorerDevelopingnewRTLandintegratingitwiththird-partyIPandmanylegacyRTLblockscanbeatime-consumingprocesswhendesignerslackafastandefficientwaytoexploreandimprovethedata,fixdesignissues,andcreateabetterstartingpointforRTLsynthesis.DCExplorerovercomestheseproblemsbyallowingyoutoperformearlyRTLexploration,leadingtoabetterstartingpointforRTLsynthesisandacceleratingdesignimplementation.DCExplorerprovidesthefollowingfeatures:•Efficientlyperformswhat-ifanalysesofvariousdesignconfigurationsearlyinthedesigncycle,evenwithincompletedesigndata,tospeedthedevelopmentofhighqualityRTLandconstraintsanddriveafaster,moreconvergentdesignflow•Generatesanearlynetlist,whichcanbeusedtobeginphysicalexplorationinICCompiler•CreatesandmodifiesfloorplansveryearlyinthedesigncyclewithaccesstoICCompilerdesignplanning•Performspreliminarysynthesisusingonlyasmallfractionofthetimeneededforfullsynthesis,yetgivesyoutimingandarearesultstypicallywithintenpercentofthefinalresultsproducedbyDesignCompilerintopographicalmodeSeeAlso•TheDCExplorerUserGuideAboutDesignVisionTheDesignVisiontoolisthegraphicaluserinterface(GUI)fortheSynopsyslogicsynthesisenvironmentandprovidesanalysistoolsforviewingandanalyzingdesignsatthegenerictechnology(GTECH)levelandgatelevel.TheDesignVisionmainwindowprovidesmenusanddialogboxesforrunningfrequentlyusedDesignCompilercommands.Italsoprovidesgraphicaldisplays,suchashistogramsandschematicsforvisualanalysis.WhenyoustartDesignVisionintopographicalmode,theDesignVisionlayoutwindowletsyouanalyzephysicalconstraints,timing,andcongestioninyourfloorplan.Alayoutviewdisplaysfloorplanconstraints,criticaltimingpaths,andcongestedareasinasingle,flatviewofthephysicaldesign.ThisinformationcanhelpyoutoguidelateroptimizationoperationsinDesignCompilerandotherSynopsystools.SeeAlso•TheDesignVisionUserGuide•DesignVisionHelpAboutHDLCompilerHDLCompilertranslatesVerilogorVHDLhardwarelanguagedescriptionsintoagenerictechnology(GTECH)netlist,whichisusedbyDesignCompilertocreateanoptimizednetlist.SeeAlso•HDLCodingforSynthesis•TheHDLCompilerdocumentationAboutDesignWareLibraryADesignWarelibraryisacollectionofreusablecircuit-designbuildingblocks,whicharetightlyintegratedintotheSynopsyssynthesisenvironment.Duringsynthesis,DesignCompilerselectstherightcomponentwiththebestspeedandareaoptimizationfromtheDesignWareLibrary.SeeAlso•TheDesignWareLibrarydocumentationAboutDFTCompilerandDFTMAXTheDFTCompilertoolistheSynopsysadvancedtestsynthesissolution.Itenablestransparentimplementationofdesign-for-testcapabilitiesintotheSynopsyssynthesisflowwithoutinterferingwithfunctional,timing,signalintegrity,orpowerrequirements.DFTMAXcompressionprovidessynthesis-basedadaptivescantechnologytolowerthecostoftestingcomplexdesigns,particularlywhenfabricatedwithadvancedprocesstechnologies.Thesedeep-submicron(DSM)designscanhavesubtlemanufacturingdefectsthatareonlydetectedbyapplyingDSMtests,suchasat-speedandbridgingtests,inadditiontostuck-attests.Theextrapatternsneededtoachievehightestqualityforthesedesignscanincreaseboththetesttimeandthetestdata,resultinginhighertestcosts.DFTMAXreducesthesecostsbydelivering10-100xtestdataandtesttimereductionwithverylowsiliconareaoverhead.DFTMAXuniquelyenablesadaptivescancompressionsynthesisinDesignCompilerandadaptivescanpatterngenerationinTetraMAXATPG.SeeAlso•TheDFTCompilerandDFTMAXdocumentationAboutLibraryCompilerLibraryCompilerreadsthedescriptionofanASIClibraryfromatextfileandcompilesthedescriptionintoeitheraninternaldatabase(.dbfileformat)orintoVHDLlibraries.Thecompileddatabasesupportssynthesistools.TheVHDLlibrariessupportVHDLsimulationtools.SeeAlso•TheLibraryCompilerdocumentationAboutPowerCompilerThePowerCompilertooloffersacompletemethodologyforpower,includinganalyzingandoptimizingdesignsforstaticanddynamicpowerconsumption.SeeAlso•PowerOptimizationinTopographicalMode•ThePowerCompilerUserGuide更多内容见附件免责声明：本页面/内容部分素材来源于互联网公开信息，旨在传递更多信息，不代表本平台立场。版权归原作者或机构所有，如涉及侵权，请通过平台联系我们，我们将在核实后第一时间处理。本平台对转载内容的真实性、准确性不作任何保证，用户需自行判断并承担使用风险。
图 1 几何模型示意图
图 2 板壳单元的雅克比分布
图 3 艏部舱段结构有限元模型
