首页/文章/ 详情

数字与定制/模拟工具通过台积电16FF+制程的认证,并与台积电合作开发10纳米FinFET工艺

2月前浏览19

Cadence数字和定制/模拟分析工具已通过台积电公司16FF+制程的V0.9设计参考手册(Design Rule ManualDRM) SPICE认证,相比于原16纳米FinFET制程,可以使系统和芯片公司通过此新工艺在同等功耗下获得15%的速度提升、或者在同等速度下省电30%。目前16FF+ V1.0认证正在进行中,计划于201411月实现。Cadence也和台积电合作实施了16FF+ 制程定制设计参考流程的多处改进。此外,Cadence也在与TSMC台积电合作10纳米FinFET制程,Cadence的技术已经为支持早期投入10纳米的定制设计做好准备.

来源:Cadence楷登
芯片Cadence
著作权归作者所有,欢迎分享,未经许可,不得转载
首次发布时间:2025-09-24
最近编辑:2月前
Cadence楷登
签名征集中
获赞 2粉丝 109文章 636课程 0
点赞
收藏
作者推荐

Packages Enable Successful IP Integration

Building a system on chip (SoC) from IP blocks requires system-level integration and bring-up, and that requires firmware working on the target. In a fast-paced development cycle, it is crucial to provide customers with IP blocks and tested firmware. In particular, at the bring-up stage, there may be very few debug capabilities at hand and, therefore, a firmware package that is pre-tested on multiple platforms and systems will speed up the integration effort. The driver package provides the following benefits:Abstracts implementation details through well-defined and use case-driven application programming interface (API)Enables early (pre-silicon) development of a board support package (BSP) / software development toolkit (SDK)Provides early reference to silicon validation.Cadence soft-IP cores now come with firmware that has been tested in simulation, on our emulation platform and on FPGA boards.来源:Cadence楷登

未登录
还没有评论
课程
培训
服务
行家
VIP会员 学习计划 福利任务
下载APP
联系我们
帮助与反馈